Control method and controller for dram

ABSTRACT

A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, asoociated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.

FIELD OF THE INVENTION

The present invention relates to a dynamic random access memory (DRAM),and more particularly, to a method for arranging a sequence of controlcommands of a DRAM.

BACKGROUND OF THE INVENTION

A DRAM has advantages of being low in cost, simple in structure, andhigh in density within unit area, and is thus commonly applied invarious consumer electronic products, e.g., a master memory of apersonal computer. An electronic device usually reads data from orwrites data to a DRAM via a memory controller. For example, to read datafrom a DRAM, a memory controller first sends an ACTIVE command,specifying a predetermined row address, for asking the DRAM to load acontent of the predetermined row to a memory bank. The memory controllerthen sends a READ command, specifying a memory bank address and a columnaddress, for acquiring the data temporarily stored in the predeterminedcolumn of the predetermined memory bank.

To optimize operation performance, in general, the memory controllerconsecutively sends a plurality of commands to the DRAM. However, noiseinterference resulted from the differences between the commands onsignal lines are not considered in the prior memory controller whensending the commands to the DRAM. For example, supposing that the memorycontroller consecutively sends two read commands to the DRAM, withaddress contents of the two commands respectively being hexadecimal0x0000 and 0xffff. Therefore, when the memory controller switches asignal at its address output end from 0x0000 to 0xffff, noises occur atsignal lines for transmitting the address content due to 16 concurrenttoggles. The greater the noise is, the more severe interference isimposed on a content of an original signal, and even cause the DRAM atthe other end of the signal lines to misjudge contents of the commands.

Despite the trend of increasing both operation efficiency and dataamount of electronic devices, the above interference becomes moredrastic along with increase of clock speed and number of signal lines.The interference may be lowered by adopting a multi-layer printedcircuit board, which however significantly increases overall hardwarecost of the electronic device, and is thus an unsatisfactory solution.

SUMMARY OF THE INVENTION

Therefore, the object of the present invention is to provide a controlmethod and controller for a DRAM. Through an appropriate arrangement ofcommand contents and command sequence transmitted to a DRAM, the methodand controller of the present invention is capable of reducing thenumber of concurrent toggles on a signal line to lower correspondingnoise interference. Hence, an electronic device implementing the methodand controller of the present invention is capable of lowering noisewhen the electronic device operates at a higher speed without increasingshields of a printed circuit board.

According to an embodiment of the present invention, a control methodfor a DRAM is provided. The method comprises judging an address contentdifference between a first command and a third command, determining aplurality of buffering address contents, associated with at least onesecond command, and sequentially transmitting the first command, the atleast one second command and the third command to the DRAM. The firstcommand and the third command are respectively a first-type command, andthe at least one second command is a second-type command.

According to another embodiment of the present invention, a controlmethod for a DRAM is provided. The method comprises identifying whetheran address content difference between a first command and a secondcommand is greater than a predetermined threshold, determining aplurality of buffering address contents, associated with at least onesecond command, according to the address content difference, andsequentially transmitting the first command, the at least one secondcommand and the third command to the DRAM. The first command and thethird command are respectively a first-type command, and the secondcommand is a second-type command.

Compared to the prior art, the control method and controller for a DRAMprovide advantages of effectively reducing noise and cost.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore readily apparent to those ordinarily skilled in the art afterreviewing the following detailed description and accompanying drawings,in which:

FIG. 1 is a flowchart of a control method according to an embodiment ofthe present invention.

FIG. 2 is a flowchart of a control method according to anotherembodiment of the present invention.

FIG. 3 is a block diagram of a controller according to an embodiment ofthe present invention.

FIG. 4 is a block diagram of a controller according to anotherembodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more specifically withreference to the following embodiments. It is to be noted that thefollowing descriptions of preferred embodiments of this invention arepresented herein for purpose of illustration and description only. It isnot intended to be exhaustive or to be limited to the precise formdisclosed.

According to address contents, commands transmitted from a memorycontroller to a DRAM are generally divided into two types. A first-typecommand comprises more address information, inferring that an addresscolumn in the first-type command has a higher utilization rate. Forexample, an ACTIVE command requesting a DRAM to load a content of apredetermined row to a memory bank includes an address of thepredetermined row, and is thus a first-type command. A WRITE command anda READ command respectively include addresses for specifying apredetermined memory bank and a column, and are thus first-typecommands. Furthermore, a module register set (MRS) command is alsoregarded as a first-type command. In contrast, a second-type commandcomprises less address information or no address information at all. Forexample, a no operation (NOP) command, a PRECHARGE command for releasingan activated predetermined row in a predetermined memory bank, and aREFRESH command for asking a DRAM to update all stored contents, aresecond-type commands.

In a control method and a controller for a memory according to anembodiment of the present invention, at least a second-type command canbe interposed between two first-type commands, acting as a buffer. Byappropriately re-arranging contents and a sequence of commandstransmitted to a DRAM, the control method and the controller for amemory according to the present invention are capable of effectivelyreducing the number of concurrent toggles occurring on signal lines toreduce corresponding noise interference.

FIG. 1 shows a flowchart of a control method according to an embodimentof the present invention. Suppose a first command and a third commandtransmitted from a control end to a DRAM are both first-type commands,comprising more address information. For example, the first command is aWRITE command and the third command is an ACTIVE command. As shown inFIG. 1, the method begins with Step S11 to judge an address contentdifference between the first command and the third command. For example,if the address contents of the first command and the third command arehexadecimal 0x0000 and 0xffff, respectively, the address contentdifference obtained in Step S11 is hexadecimal 0xffff.

Subsequently, in Step S12, a buffering address content of a secondcommand is determined according to the address content difference (i.e.0xffff). For example, the second command is a PRECHARGE command. Inpractice, the PRECHARGE command only utilizes few bits in its addresscolumn to assign an address of a memory bank to be pre-charged. Afterreceiving a PRECHARGE command, the DRAM usually reads only the addresscontent for assigning the memory bank, and ignores contents of otheraddress columns in the PRECHARGE command. In this embodiment, a content,acting as a buffer, can be filled into the address columns ignored bythe DRAM. For example, supposing that an address content of the secondcommand is originally hexadecimal 0x3000, wherein the last three digits000 (corresponding to 12 bits) represent column addresses to be ignored.In Step S12, the address content of the second command may be modifiedto 0x30ff, as the buffering address content. In Step S13, the firstcommand, the second command and the third command are sequentiallytransmitted to the DRAM.

As an example, suppose the address column contents of the first, secondand third commands are respectively hexadecimal 0x0000, 0x30ff and0xffff. If the first and third commands are transmitted in sequence,noise resulted from 16 concurrent toggles occurs on signal linestransmitting the address contents when the memory controller switches asignal at its output end from 0x0000 to 0xffff. According to the aboveembodiment of the present invention, the signal on the signal lines fortransmitting the address contents first switches from 0x0000 to 0x30ff,causing only 10 toggles. The address signal then switches from 0x30ff to0xffff, causing only 6 toggles. It is concluded that the number ofconcurrent toggles occurred during each command switching is less afterthe second command is interposed between the first and third commandsthan that when directly transmitting the first and third commands insequence.

Take another example where another READ command (which also belongs tothe foregoing first-type command) is to be transmitted at the controlend after the third command, and the address column content of the readaddress is 0x000f. According to the control method in FIG. 1, asecond-type command, e.g., a NOP command, is interposed between thethird command and the READ command by the control end and an addresscolumn content of the NOP command is designated to be 0xf00f accordingto an address content difference between the two commands, i.e. thethird command and the READ command. Thus, a signal on the signal linesfor transmitting an address content is switched from 0xffff to 0xf00f,and then from 0xf00f to 0x000f. The numbers of the concurrent togglesresulted from the two switchings are 8 and 4 respectively, which areboth less than the 12 toggles occurred when directly switching theaddress signal from 0xffff to 0x000f.

It is to be noted that, since the last three digits of 0x3xff in thesecond command are not considered by the DRAM, modifying the addresscontent of the second command to 0x30ff causes no effects in controllingthe DRAM. Similarly, the address column content of the above NOP commandis not considered by the DRAM, so that modifying the address columncontent to 0xf00f causes no effects in controlling the DRAM, either.

From the previous two examples, the commands transmitted from thecontrol end to the DRAM are sequentially the READ command, the PRECHARGEcommand, the ACTIVE command, the NOP command, and the READ command,whose contents are respectively 0x0000, 0x30ff, 0xffff, 0xf00f, and0x000f. It is observed that, between every two first-type commands atleast a second-type command comprising an appropriate address columncontent for providing a buffering effect is interposed. With the controlmethod of the present invention, the number of concurrent togglesoccurring on signal lines is reduced to lower correspondingly noiseinterference. Therefore, an electronic device implementing the presentinvention is capable of operating at higher speeds without increasingshields of printed circuit boards to lower noise. In practice, thecommands transmitted to the DRAM and the address contents are notlimited in the examples described above.

In other embodiments of the present invention, apart from the addresscontent difference between the first command and the third command, aconfiguration of signal lines associated with the DRAM may also serve asa reference for determining the buffering address contents. For example,before determining the contents of which address columns are to bemodified, physical distances and neighboring relationships between theaddress signal lines are taken into consideration to prevent togglessimultaneously occurring at two neighboring signal lines, so as tofurther lower noise interference resulted by coupling of the signallines. Moreover, since a power line (including a ground line) provides acertain signal isolating effect, noise caused by simultaneously changingvoltages of address signal lines at the opposite sides of a power lineis also less than that without a power line in between. Therefore, aconfiguration of power lines on a printed circuit board or in a chip mayalso serve as a reference when determining the buffering addresscontents.

FIG. 2 shows a flowchart of a control method according to anotherembodiment of the present invention. The method begins with Step S21 toidentify whether an address content difference between a first commandand a third command, to be sequentially transmitted to a DRAM, isgreater than a predetermined threshold. When a determination result ofStep S21 is affirmative, Step S22 is performed to determine a bufferingaddress content of a second command. In Step S23, the first command, thesecond command and the third command are sequentially transmitted to theDRAM. Conversely, when the result from Step S21 is negative, Step S24 isperformed to directly transmit the first command and the third commandto the DRAM in sequence.

A main difference between the embodiments respectively shown in FIG. 1and FIG. 2 is that, the interposing of the second command is optional inthe embodiment shown in FIG. 2. In the event that the address contentdifference between the two first-type commands (i.e., the first andthird commands) is rather insignificant, that is to say, an excessivenumber of toggles are unlikely to be caused by directly transmitting thetwo commands in sequence. Consequently, the interposing of a second-typecommand between the two first-type commands is not an absolutelynecessary step. For example, in Step S21, a determination condition maybe whether the number of toggles corresponding to the address contentdifference is greater than 8, or directly determining whether theaddress content difference is greater than a predetermined hexadecimalnumber, and thereby effectively controlling the number of toggles.Similar to the embodiment in FIG. 1, in the embodiment in FIG. 2, aconfiguration of signal lines associated with the DRAM or aconfiguration of power lines may also serve as a reference fordetermining the buffering address content in Step S22.

Please note that some constraints have to be put on a control method forrearranging contents and sequence of commands transmitted to a DRAM,according to the present invention. While moving forward a subsequentsecond-type command to be interlaced with first-type commands, thecontrol method must assure that the rearranged command sequence alsocomply with the specification of DRAM, such as the maximum time intervallimitation of the REFRESH command. In addition, while moving forward aPRECHARGE command, which releases a specific activated row of adesignated memory bank, the control method must assure that thePRECHARGE command cannot be moved to any place ahead of a WRITE commandor a READ command operated on the same memory bank.

FIG. 3 shows a block diagram of a controller for a DRAM according to anembodiment of the present invention. A controller 30, for controlling aDRAM 60, comprises a first judging module 32, a determination module 34and a transmission module 36. In practice, the controller 30 maycomprise other circuit elements not shown in FIG. 3. The first judgingmodule 32 judges an address content difference between a first commandand a third command. The determination module 34 determines a bufferingaddress content of a second command according to the address differentcontent. After the determination module 34 determines the bufferingaddress content of the second command, the transmission module 36sequentially transmits the first command, the second command and thethird command to the DRAM 60. Operations of the controller 30 are asdescribed with reference to FIG. 1, and shall be omitted for brevity.

FIG. 4 shows a block diagram of a controller for a DRAM according toanother embodiment of the present invention. A controller 40, forcontroller a DRAM 60, comprises a second judging module 42, adetermination module 44 and a transmission module 46. In practice, thecontroller 40 may comprise other circuit elements not shown in FIG. 4.The second judging module 42 judges whether an address contentdifference between a first command and a third command is greater than apredetermined threshold. When the address content difference is greaterthan the predetermined threshold, the determination module 44 determinesa buffering address content of a second command according to the addresscontent difference. After the determination module 44 determines thebuffering address content of the second command, the transmission module46 sequentially transmits the first command, the second command and thethird command to the DRAM 60. Conversely, when the address contentdifference is smaller than the predetermined threshold, the transmissionmodule 46 directly transmits the first command and the third command tothe DRAM 60 in sequence. Operations of the controller 40 are asdescribed with reference to FIG. 2, and shall be omitted for brevity.

Therefore, through an appropriate arrangement of command contents andcommand sequence transmitted to a DRAM, the method and controller of thepresent invention is capable of reducing the number of concurrenttoggles on signal lines to lower corresponding noise interference tolower noise and at the same time increase stability of signaltransmission. Thus, an electronic device applying the method andcontroller of the present invention can operate at a higher speedwithout increasing shields of an expensive printed circuit board, so asto reinforce durability of the electronic device operating at a highersystem speed and reducing cost of a printed circuit board.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiment. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

1. A control method for a dynamic random access memory (DRAM),comprising: judging an address content difference between a firstcommand and a third command; determining a plurality of bufferingaddress contents, associated with at least one second command, accordingto the address content difference; and sequentially transmitting thefirst command, the at least one second command and the third command tothe DRAM; wherein, each of the first command and the third command is afirst-type command, and the at least one second command is a second-typecommand.
 2. The control method according to claim 1, wherein thefirst-type command is a command capable of utilizing all address contentbits, and the second-type command is a command utilizing partial or noneof address content bits.
 3. The control method according to claim 2,wherein the command capable of utilizing all address content bitscomprises a mode register set (MRS) command, an ACTIVE command, a WRITEcommand and a READ command, the command utilizing partial or none of theaddress content bits comprises an update command, a no operation (NOP)command and a PRECHARGE command.
 4. The control method according toclaim 1, wherein determining the plurality of buffering address contentscomprises referencing a configuration of signal lines associated withthe DRAM or a configuration of power lines to determine the bufferingaddress contents.
 5. The control method according to claim 1, wherein atransmission sequence and contents of the first command, the secondcommand and the third command comply with specifications of DRAM.
 6. Acontrol method for a dynamic random access memory (DRAM), comprising:identifying whether an address content difference between a firstcommand and a third command is greater than a predetermined threshold;determining a plurality of buffering address contents, associated withat least one second command, according to the address content differencewhen the address content difference is greater than the predeterminedthreshold; and sequentially transmitting the first command, the secondcommand and the third command to the DRAM; wherein, each of the firstcommand and the third command is a first-type command, and the at leastone second command is a second-type command.
 7. The control methodaccording to claim 6, further comprising: sequentially transmitting thefirst command and the third command to the DRAM when the address contentdifference is smaller than the predetermined threshold.
 8. The controlmethod according to claim 6, wherein the first-type command is a commandcapable of utilizing all address content bits, and the second-typecommand is a command utilizing partial or none of the address contentbits.
 9. The control method according to claim 8, wherein the commandutilizing all address content bits comprises a mode register set (MRS)command, an ACTIVE command, a WRITE command and a READ command, thecommand utilizing partial or none of the address content bits comprisesan update command, a no operation (NOP) command and a PRECHARGE command.10. The control method according to claim 6, wherein the determiningstep determines the plurality of buffering address contents of at theleast one second command according to the address content differencewhen the address content difference is greater than the predeterminedthreshold by referencing a configuration of signal lines associated withthe DRAM or a configuration of power lines.
 11. The control methodaccording to claim 6, wherein a transmission sequence and transmittedcontents of the first command, the second command and the third commandcomply with specifications of DRAM.
 12. A controller for a DRAM,comprising: a judging module, for judging an address content differencebetween a first command and a third command; a determination module, fordetermining a plurality of buffer address contents, associated with atleast one second command, according to the address content difference;and a transmission module, for sequentially transmitting the firstcommand, the at least one second command and the third command to theDRAM; wherein, each of the first command and the third command is afirst-type command, and the at least one second command is a second-typecommand.
 13. The controller according to claim 12, wherein thefirst-type command is a command capable of utilizing all address contentbits, and the second-type command is a command utilizing partial or noneof the address content bits.
 14. The controller according to claim 13,wherein the command utilizing all address content bits comprises a moderegister set (MRS) command, an ACTIVE command, a WRITE command and aREAD command, the command utilizing partial or none of the addresscontent bits comprises an update command, a no operation (NOP) commandand a PRECHARGE command.
 15. The controller according to claim 12,wherein the determining module determines the plurality of bufferingaddress contents of at the least one second command according to theaddress content difference by referencing a configuration of signallines associated with the DRAM or a configuration of power lines. 16.The controller according to claim 12, wherein the judging module furthercomprises a predetermined threshold and identifies whether the addresscontent difference is greater than the predetermined threshold.
 17. Thecontroller according to claim 16, wherein the determining moduledetermines the plurality of buffering address contents of the at leastone second command when the address content difference is greater thanthe predetermined threshold.
 18. The controller according to claim 16,wherein the transmitting module sequentially transmits the first commandand the third command to the DRAM when the address content difference issmaller than the predetermined threshold.
 19. The controller accordingto claim 16, wherein the first-type command is a command utilizing alladdress content bits, and the second-type command is a command utilizingpartial or none of the address content bits.
 20. The controlleraccording to claim 16, wherein the determining module determines theplurality of buffering address contents by further referencing aconfiguration of signal lines associated with the DRAM or aconfiguration of power lines.